1. Field of the Invention
The present invention relates to a carrier, a coreless packaging substrate, and methods for manufacturing the same and, more particularly, to a carrier used for manufacturing a coreless packaging substrate and a manufacturing method thereof, and a coreless packaging substrate manufactured by using the carrier, and a manufacturing method thereof.
2. Description of Related Art
As the electronics industry continues to develop rapidly, the technology of semiconductor packaging accordingly moves towards high integration and miniaturization. In order to meet the demands such as multifunction and high efficiency in electronic devices, packaging substrates, for active and passive components, having many wiring connections thereon have advanced from being single-layered boards to multiple-layered boards. Hence, the space for wiring layout in a limited packaging substrate can be expanded to meet the demand of the application of high-density integrated circuits.
With regard to a conventional process of manufacturing semiconductor devices, a common manufacturer of chip loaders first produces suitable chip loaders for semiconductor devices, such as packaging substrates or leadframes. Then, the chip loaders are processed with semiconductor chip attachment, wire bonding, molding, implanting solder balls etc. for completion of semiconductor devices. In detail, a chip is adhered via its back surface to the top surface of a packaging substrate and then electrically connected thereto by wire bonding. Alternatively, a chip is electrically connected via its active surface to the top surface of a packaging substrate by the flip chip technique, followed by underfilling performed between the semiconductor chip and the packaging substrate to protect the electrical connections and to strengthen mechanical connections therebetween. Finally, electrical connections to other electronic devices are achieved by disposing solder balls on the back surface of the substrate.
The abovementioned chip loaders can have a core layer or be a coreless packaging substrate. With reference to FIGS. 1A to 1G, a flowchart shows manufacturing of a conventional coreless packaging substrate. First, as shown in FIGS. 1A and 1B, a carrier 10 is provided and a first dielectric layer 11 is laminated on the carrier 10. Then, a first wiring layer 15 is formed on the first dielectric layer 11, and has a plurality of conductive lands 15a. As shown in FIGS. 1C and 1D, a built-up structure 16 is formed on the first dielectric layer 11 and the first wiring layer 15, and includes a second dielectric layer 161, a second wiring layer 162 disposed on the second dielectric layer 161, and a plurality of conductive vias 163 disposed in the second dielectric layer 161. The built-up structure can have an increased number of layers if necessary.
Subsequently, as shown in FIG. 1E, the carrier 10 underneath the first dielectric layer 11 is removed. Solder masks 17 and 17′ are formed respectively on the uncovered surface of the dielectric layer 11—being revealed owing to the removal of the carrier 10—and on the outermost dielectric layer 161 and second wiring layer 162 of the built-up structure 16. Openings 174′ are formed in the solder mask 17′. Conductive vias 18a connecting to the conductive lands 15a are formed in the dielectric layer 11, and conductive pads 18b connected to the conductive lands 15a through the conductive vias 18a are formed in openings 174′. Then, openings 174 are formed in the solder mask 17 to expose the first conductive pads 162a. Finally, as shown in FIG. 1G, a surface finish layer 19 is formed on the second conductive pads 18b and the first conductive pads 162a, to thereby obtain a coreless packaging substrate. As shown in FIGS. 1A to 1G, the conventional method is not advantageous to increase the productivity since the coreless packaging substrate can be manufactured only on one side of the carrier 10. Additionally, it is commonly difficult for the carrier 10 underneath the first dielectric layer 11 to be removed from the coreless packaging substrate.
Furthermore, as the trend of the packaging substrate is towards fine pitch, the size of the pads decreases such that the dimension of the openings of the solder mask for exposing the pads also reduces. When the dimension of the openings 174′ of the solder mask 17′ at the chip bonding side decreases to 50 μm or less, the current photolithography as exposure and development can not exhibit good performance. Moreover, when the solder bumps are formed by stencil printing on the second conductive pads 18b, the decreased dimension of the openings 174′ commonly results in voids formed under the solder bumps. Simultaneously, the joint strength between the surface finish layer 19 and the solder weakens due to the reduced joint area. Besides, the aforesaid coreless packaging substrate, without support by a core layer, can not show sufficient rigidity, and thus easily incurs warpage, resulting in poor reliability.
Therefore, it is desirable to provide a coreless packaging substrate and a method for manufacturing the same to lower the possibility of the warpage, to reduce the material consumption, to decrease the costs, and also to improve the reliability.